1. Field of the Invention
The present invention relates to a data slicer with a source-degeneration structure. In particular, this invention can be implemented in a FM demodulation system. It is located at the end of the demodulator, the data slicer can slice a signal transmitted through air and demodulate the same with a demodulator to produce a frequency-shifted modulation (FSK) signal. The signal is a perfect square-wave and is provided to a base band circuit.
2. Description of the Related Art
The image data or the data transmitted by a digital method is modulated to a square-wave signal before the signal is transmitted and is transmitted to the receiver through a specified medium. Usually, the high frequency signal is deformed after the frequency-shifted modulation (FSK) signal is transmitted by the air and is demodulated by the demodulator. The reference voltage of the modulation signal is not correctly obtained because the modulation signal is deformed and the circuit can't produce a square-wave with a 50% duty cycle. Therefore, the data slicer needs to produce a perfect square-wave signal for the base band circuit later.
FIG. 1 shows a conventional data slicer that uses a pluirality of series resistors to produce a reference voltage. The data slicer comprises a plurality of resistors R11, R12, R13, R1n, a bias-voltage threshold switching apparatus 10 and a buffer 12 comprising an amplifier. The drawbacks are that the bias-voltage of the output signal is needed and the reference voltage is not located in the center level when the input signal is small.
FIG. 2 shows a prior circuit that uses a received signal spectrum detecting (RSSI) circuit and a low pass filter to obtain an average value of the input signal as well as a reference voltage for a data slicer. The circuit comprises a received signal spectrum detecting (RSSI) circuit 16, a resistor R21 and a capacitor C21. The drawback is that the circuit averages the signal and the noise signal when the signal is small and increases the reference voltage.
FIG. 3 shows a prior circuit that uses a received signal spectrum detecting (RSSI) circuit to obtain the spectrum of the input signal and subtracts 6 dB to provide a reference voltage. This is called a peak detector method. The circuit comprises a RSSI circuit 20, a capacitor C31 and a decreasing 6 dB circuit including a transistor T31, a resistor Rd1 and a current source Id1. The drawback is that the method detects the disturbance peak and sees it as a high level when the low level signal has a disturbance peak. Therefore, the method obtains the wrong reference voltage.
U.S. Pat. No. 6,734,918, entitled “Data Slicer Circuit”, provides a data slicer circuit, and is illustrated in FIG. 4. The data slicer comprises a capacitor C1 for receiving the image signal, a clamping circuit 24 for receiving the image signal by a current coupling method, a first settle capacitor C2 for holding the voltage of the image signal, a second settle capacitor C3 for obtaining the average voltage of the image signal within a fixed period and holding the average voltage, a comparator 26 for comparing the above two holding voltage and outputting a signal when the holding voltage of the second capacitor C3 is greater than the holding voltage of the first capacitor C1. However, this method needs a coupling capacitor to prevent the direct voltage of the front end from affecting the operation voltage of data slicer. At the same time, the capacitor value is big for preventing signal deformation, and this will increase the difficulty of manufacture of the IC and require a large capacitor. Besides, this method obtains the reference voltage by charging and discharging the capacitor. The above method obtains the wrong reference voltage when the circuit deals with a high frequency signal due to the capacitor charging and discharging incompletely.